Ggtcf

I'm writing a verilog module for my CompSci class and this module specifically is the data memory module. Structurally and analytically, I'm looking at it and it should work based off of the other files that I have, but I'm not sure why this one specifically is acting up and giving me all x's. Hoping a fresh set of eyes can help find the error I missed. Thanks in advance.

datamem.v:

module datamem(Ina, Inb, enable, readwrite, dataOut, clk, rst);

input wire [31:0] Ina;
input wire [31:0] Inb;
input wire enable;
input wire readwrite;
input wire clk;
input wire rst;

reg [31:0] memory[0:65535];
output reg [31:0] dataOut;

always @(memory[Ina]) begin
 dataOut = memory[Ina];
 end

always @(posedge clk) begin
 if(1'b1 == readwrite) begin
 memory[Ina] = Inb;
 end
end

endmodule

datamem_tb.v:

module datamem_tb();

reg [31:0] Ina;
reg [31:0] Inb;
reg enable;
reg readwrite;
reg clk;
reg rst;

wire [31:0] dataOut;

datamem DUT (Ina, Inb, enable, readwrite, dataOut, clk, rst);

initial
begin

 Ina <= 32'd0;
 Inb <= 32'd0;
 enable <= 0;
 readwrite <= 0;

 #20 Ina <= 32'd1234;
 #20 Inb <= 32'd1234;
 #20 Ina <= 32'd0517;
 #20 Inb <= 32'd10259;

end

always @(Ina or Inb)
 #1 $display("| Ina = %d | Inb = %d | dataOut = %d |", Ina, Inb, dataOut);

endmodule

A few things as to why you are getting all 'x:

1. You never run the clock, you need to add something like the following to have the clock toggle:

 initial begin
 clk = 1'b0;
 forever #5 clk = ~clk;
 end

2. You never assert readwrite which is required to write to your memory module (you set it to 0 on line 20 and never change it). Without being written to, memory will retain its original value of 'x for every element

Aside from that, there are a few other issues with your module:

1. Use implicit sensitive lists (instead of always @(memory[inA]) use always @(*))


2. Use non-blocking assignment for your memory write (memory[inA] <= inB)


3. Consider using $monitor instead of $display for your print statements to avoid timing issues, and you only need call it at the beginning of your initial block in your testbench (http://referencedesigner.com/tutorials/verilog/verilog_09.php)


4. Your rst and enable arent connected to anything.

Another example of a memory unit implementation can be found here:
Data memory unit