Atlas-SoC board preloader troubleshootingPreloading CSS ImagesFlash preloader: Not preloading properly?preloader with jqueryData Corruption when Segregating Functions into Different FilesFDT and ATAGS support not compiled in - hanging ### ERROR ### Please RESET the board ###DE1-SoC Board FPGA for evolvable hardwareBare-Metal Interrupt Handling on Lego Mindstorm EV3 (TexasInstruments Sitara AM1808 SoC)Access violation while compiling (synthesis step) in Quartus II with Qsys SystemHow to run baremetal application on Altera Cyclone V SoC using HPS loading from SD cardCan't build bootlader and kernel image for my DE0-Nano-SoC board
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Atlas-SoC board preloader troubleshooting
Preloading CSS ImagesFlash preloader: Not preloading properly?preloader with jqueryData Corruption when Segregating Functions into Different FilesFDT and ATAGS support not compiled in - hanging ### ERROR ### Please RESET the board ###DE1-SoC Board FPGA for evolvable hardwareBare-Metal Interrupt Handling on Lego Mindstorm EV3 (TexasInstruments Sitara AM1808 SoC)Access violation while compiling (synthesis step) in Quartus II with Qsys SystemHow to run baremetal application on Altera Cyclone V SoC using HPS loading from SD cardCan't build bootlader and kernel image for my DE0-Nano-SoC board
I just bought a new Cyclone V board from Terasic ( Atlas-SoC ) and planned to build a bare metal application. At first, I used the GSRD provided by Terasic. The example project is from version 14.0 and my 17.1 Quartus asked me to launch an update to those 14.0 IP, but I saw that they already compile everything and I had a handoff file folder. All I needed to do was just make a preloader and uboot. Then I followed these steps (from rocketboard and many places else):
- Generate .rbf file.
- I made a preloader using the bsp-editor tool from EDS-SoC.
- Compile successfully the preloader and obtain
preloader-mkpimage.bin. - Generate uboot and also uboot script file.
- Load preloader into SD card using alt-boot-disk-util.
- Copy all the rbf file, uboot and uboot script to an SD card. At this moment I did not make any application because I wanted to check if the preloader loaded or not.
- Plug SD card into the board and then power up 8. In Putty, I saw the U-boot spl and Uboot worked fine.
With the first success, I tried to make my own HPS-FPGA design. I based on HPS configuration to make my own HPS ( initialize I2C, UART, no sdram, etc. ). For the FPGA part, I put some LEDs PIO, JTAG UART, System ID peripheral, etc.
After finish my Platform designer ( Qsys), I made a VHDL top file and connect all the nodes ( just like GSRD design). At this point, I did not add any IP such as HPS reset, debounce, etc. because I just wanted to see if the preloader worked or not.
Then I followed exactly those steps as I did with GSRD design, however this time on Putty I received nothing. U-Boot SPL did not even appear. Feeling weird, I came back to GSRD to check. I copied the whole folder of GSRD design and made it my own new project. Then I launched an update for those IP and compiled the whole thing again. After that, preloader and uboot were made in the same steps and the result amazed me: On Putty terminal, I only had this single line
U-Boot SPL 2013.01.01 (Mar 08 2019 - 10:28:04)
and nothing else happened. I think that something wrong with the preloader, it has something mismatched with my Quartus design or I have made mistakes during building the preloader.
I have searched in a lot of places, came up with many hypotheses, and tried to fix this. I even contacted Terasic and visited the Intel community forum, but I still haven't got an answer.
preloader altera bare-metal
edited Mar 8 at 10:30
Ganesa Vijayakumar
5914825
asked Mar 8 at 10:09
Giant BananaGiant Banana
34
add a comment |
I just bought a new Cyclone V board from Terasic ( Atlas-SoC ) and planned to build a bare metal application. At first, I used the GSRD provided by Terasic. The example project is from version 14.0 and my 17.1 Quartus asked me to launch an update to those 14.0 IP, but I saw that they already compile everything and I had a handoff file folder. All I needed to do was just make a preloader and uboot. Then I followed these steps (from rocketboard and many places else):
- Generate .rbf file.
- I made a preloader using the bsp-editor tool from EDS-SoC.
- Compile successfully the preloader and obtain
preloader-mkpimage.bin. - Generate uboot and also uboot script file.
- Load preloader into SD card using alt-boot-disk-util.
- Copy all the rbf file, uboot and uboot script to an SD card. At this moment I did not make any application because I wanted to check if the preloader loaded or not.
- Plug SD card into the board and then power up 8. In Putty, I saw the U-boot spl and Uboot worked fine.
With the first success, I tried to make my own HPS-FPGA design. I based on HPS configuration to make my own HPS ( initialize I2C, UART, no sdram, etc. ). For the FPGA part, I put some LEDs PIO, JTAG UART, System ID peripheral, etc.
After finish my Platform designer ( Qsys), I made a VHDL top file and connect all the nodes ( just like GSRD design). At this point, I did not add any IP such as HPS reset, debounce, etc. because I just wanted to see if the preloader worked or not.
Then I followed exactly those steps as I did with GSRD design, however this time on Putty I received nothing. U-Boot SPL did not even appear. Feeling weird, I came back to GSRD to check. I copied the whole folder of GSRD design and made it my own new project. Then I launched an update for those IP and compiled the whole thing again. After that, preloader and uboot were made in the same steps and the result amazed me: On Putty terminal, I only had this single line
U-Boot SPL 2013.01.01 (Mar 08 2019 - 10:28:04)
and nothing else happened. I think that something wrong with the preloader, it has something mismatched with my Quartus design or I have made mistakes during building the preloader.
I have searched in a lot of places, came up with many hypotheses, and tried to fix this. I even contacted Terasic and visited the Intel community forum, but I still haven't got an answer.
preloader altera bare-metal
edited Mar 8 at 10:30
Ganesa Vijayakumar
5914825
asked Mar 8 at 10:09
Giant BananaGiant Banana
34
add a comment |
I just bought a new Cyclone V board from Terasic ( Atlas-SoC ) and planned to build a bare metal application. At first, I used the GSRD provided by Terasic. The example project is from version 14.0 and my 17.1 Quartus asked me to launch an update to those 14.0 IP, but I saw that they already compile everything and I had a handoff file folder. All I needed to do was just make a preloader and uboot. Then I followed these steps (from rocketboard and many places else):
- Generate .rbf file.
- I made a preloader using the bsp-editor tool from EDS-SoC.
- Compile successfully the preloader and obtain
preloader-mkpimage.bin. - Generate uboot and also uboot script file.
- Load preloader into SD card using alt-boot-disk-util.
- Copy all the rbf file, uboot and uboot script to an SD card. At this moment I did not make any application because I wanted to check if the preloader loaded or not.
- Plug SD card into the board and then power up 8. In Putty, I saw the U-boot spl and Uboot worked fine.
With the first success, I tried to make my own HPS-FPGA design. I based on HPS configuration to make my own HPS ( initialize I2C, UART, no sdram, etc. ). For the FPGA part, I put some LEDs PIO, JTAG UART, System ID peripheral, etc.
After finish my Platform designer ( Qsys), I made a VHDL top file and connect all the nodes ( just like GSRD design). At this point, I did not add any IP such as HPS reset, debounce, etc. because I just wanted to see if the preloader worked or not.
Then I followed exactly those steps as I did with GSRD design, however this time on Putty I received nothing. U-Boot SPL did not even appear. Feeling weird, I came back to GSRD to check. I copied the whole folder of GSRD design and made it my own new project. Then I launched an update for those IP and compiled the whole thing again. After that, preloader and uboot were made in the same steps and the result amazed me: On Putty terminal, I only had this single line
U-Boot SPL 2013.01.01 (Mar 08 2019 - 10:28:04)
and nothing else happened. I think that something wrong with the preloader, it has something mismatched with my Quartus design or I have made mistakes during building the preloader.
I have searched in a lot of places, came up with many hypotheses, and tried to fix this. I even contacted Terasic and visited the Intel community forum, but I still haven't got an answer.
preloader altera bare-metal
edited Mar 8 at 10:30
Ganesa Vijayakumar
5914825
asked Mar 8 at 10:09
Giant BananaGiant Banana
34
I just bought a new Cyclone V board from Terasic ( Atlas-SoC ) and planned to build a bare metal application. At first, I used the GSRD provided by Terasic. The example project is from version 14.0 and my 17.1 Quartus asked me to launch an update to those 14.0 IP, but I saw that they already compile everything and I had a handoff file folder. All I needed to do was just make a preloader and uboot. Then I followed these steps (from rocketboard and many places else):
- Generate .rbf file.
- I made a preloader using the bsp-editor tool from EDS-SoC.
- Compile successfully the preloader and obtain
preloader-mkpimage.bin. - Generate uboot and also uboot script file.
- Load preloader into SD card using alt-boot-disk-util.
- Copy all the rbf file, uboot and uboot script to an SD card. At this moment I did not make any application because I wanted to check if the preloader loaded or not.
- Plug SD card into the board and then power up 8. In Putty, I saw the U-boot spl and Uboot worked fine.
With the first success, I tried to make my own HPS-FPGA design. I based on HPS configuration to make my own HPS ( initialize I2C, UART, no sdram, etc. ). For the FPGA part, I put some LEDs PIO, JTAG UART, System ID peripheral, etc.
After finish my Platform designer ( Qsys), I made a VHDL top file and connect all the nodes ( just like GSRD design). At this point, I did not add any IP such as HPS reset, debounce, etc. because I just wanted to see if the preloader worked or not.
Then I followed exactly those steps as I did with GSRD design, however this time on Putty I received nothing. U-Boot SPL did not even appear. Feeling weird, I came back to GSRD to check. I copied the whole folder of GSRD design and made it my own new project. Then I launched an update for those IP and compiled the whole thing again. After that, preloader and uboot were made in the same steps and the result amazed me: On Putty terminal, I only had this single line
U-Boot SPL 2013.01.01 (Mar 08 2019 - 10:28:04)
and nothing else happened. I think that something wrong with the preloader, it has something mismatched with my Quartus design or I have made mistakes during building the preloader.
I have searched in a lot of places, came up with many hypotheses, and tried to fix this. I even contacted Terasic and visited the Intel community forum, but I still haven't got an answer.
preloader altera bare-metal
preloader altera bare-metal
edited Mar 8 at 10:30
Ganesa Vijayakumar
5914825
asked Mar 8 at 10:09
Giant BananaGiant Banana
34
edited Mar 8 at 10:30
Ganesa Vijayakumar
5914825
asked Mar 8 at 10:09
Giant BananaGiant Banana
34
edited Mar 8 at 10:30
Ganesa Vijayakumar
5914825
edited Mar 8 at 10:30
Ganesa Vijayakumar
5914825
edited Mar 8 at 10:30
Ganesa Vijayakumar
5914825
5914825
asked Mar 8 at 10:09
Giant BananaGiant Banana
34
asked Mar 8 at 10:09
Giant BananaGiant Banana
34
asked Mar 8 at 10:09
Giant BananaGiant Banana
34
34
add a comment |
add a comment |
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